Semiconductor Manufacturing: Wafer to Chip Process Guide

Quick Reference

The cheat within the cheat

Stage	What it changes	Typical tool / example	Main failure mode or gotcha
Wafer prep	Turns a silicon crystal into a flat, polished substrate ready for patterning.	300 mm wafer; saw, lap, polish, clean.	Surface defects become permanent yield loss; a perfect layout cannot rescue a dirty wafer.
Oxidation / nitridation	Grows or modifies insulating and barrier films on silicon.	Thermal oxidation furnace for SiO2 on a gate stack.	Not every film is deposited. Some critical films are grown, and the temperature budget matters.
Deposition	Adds dielectric or metal layers to build device structures.	CVD, ALD, or PVD for high-k, tungsten, copper seed, and liners.	Pick ALD for conformality, CVD for throughput, and PVD when line-of-sight metal is enough.
Lithography	Transfers the pattern from mask/reticle to photoresist.	ArF immersion DUV for many layers; EUV for the hardest layers.	Overlay, focus, and stochastic resist failures can break yield before the feature size does.
Etch	Removes exposed material to leave patterned structures.	Plasma etch, reactive ion etch, deep reactive ion etch.	Too isotropic and you widen features; too aggressive and you damage sidewalls.
Implant / doping	Introduces ions that change conductivity and junction depth.	Boron, arsenic, phosphorus implants; up to about 60 implants in a CMOS IC with embedded memory.	Implant damage and amorphization need a controlled anneal afterward.
Anneal	Activates dopants and repairs crystal damage through heat.	Rapid thermal processing or laser anneal.	Too much heat broadens junctions and ruins the scale you just created.
CMP	Flattens the wafer so the next layer can print predictably.	Chemical mechanical planarization with slurry and pad.	Dishing and erosion can distort metal resistance and ruin interconnect timing.
Metrology / inspection	Measures dimensions, overlay, film thickness, and defects.	Overlay metrology, defect inspection, CD-SEM, reticle QC.	You cannot tune what you do not measure; process control is a feedback loop, not an afterthought.
Interconnect	Builds the wiring stack that actually connects the transistors.	Copper damascene, vias, low-k dielectrics, backside power delivery.	RC delay often dominates speed before transistor physics does.
Packaging	Turns bare die into a usable system component.	Wire bond, flip-chip, fan-out, 2.5D interposer, 3D chiplet stack.	Thermal and test complexity can erase the advantage of a smaller node.
Test / binning	Separates fully good dies from slower or partially disabled parts.	Wafer sort, final test, binning for clocks, power, and defects.	A good-looking wafer can still produce split bins because variation and packaging stress surface later.

Mental Model

What a fab is really doing

1. A chip is a stack of patterned layers

Semiconductor manufacturing is layer-by-layer image transfer plus material modification. The wafer is the canvas, the mask or reticle is the blueprint, and each cycle changes only a thin slice of the structure.

Example: ASML notes that the full chip patterning loop can repeat 100 times or more; one layer may use EUV while the next uses DUV, etch, deposition, and CMP to build the real 3D structure.

2. Node labels are generations, not literal dimensions

TSMC N2, Intel 18A, and Samsung SF2 are all leading-edge platforms, but the label is a product-generation name, not a direct promise that one company’s "2 nm" equals another’s.

Gotcha: compare transistor structure, power delivery, density, and ecosystem support before comparing the label alone.

Wafer

A polished silicon disk that carries thousands of copies of the same design.

Example: a 300 mm wafer is the dominant high-volume format in advanced logic and memory.

Die

An individual chip cut from the wafer after fabrication and test.

Example: a GPU package may hold several large dies plus HBM stacks.

Reticle / mask

The pattern blueprint used by lithography to print a layer on the wafer.

Gotcha: EUV reticles are reflective multilayer mirrors and need vacuum exposure.

Manufacturing Flow

From crystal to finished wafers

The same sequence repeats many times. In practice, the exact order varies by device type, but the control loop stays the same: pattern, modify, measure, planarize, and repeat.

Step	Definition	Concrete example	Why it matters
Crystal growth	Pulls a single-crystal silicon ingot from molten silicon.	Monocrystalline silicon for a 300 mm wafer supply chain.	Crystal defects and oxygen content become upstream yield and reliability problems.
Wafer slicing and polish	Cuts the ingot into wafers and makes them mirror-flat.	Diamond saw, lapping, and chemical-mechanical polishing before fab entry.	Bow, warp, and surface roughness affect overlay and lithography focus.
Clean and prime	Removes particles and prepares the surface for film growth.	Wet clean plus dehydration bake before oxidation or deposition.	Contamination control is not housekeeping; it is yield protection.
Oxidation / nitridation	Grows insulating or barrier films directly on the silicon surface.	Thermal oxide in a furnace for gate or isolation work.	Growing a film is different from depositing one; the thermal budget is the constraint.
Deposition	Adds a new material layer, often conformally.	CVD for oxide, ALD for a thin high-k gate dielectric, PVD for a metal seed.	Choice of deposition method determines step coverage, throughput, and cost.
Photoresist coat / expose / develop	Forms the temporary stencil that defines where the next material change occurs.	ArF immersion exposure for a critical transistor layer, then develop the resist image.	Resist chemistry and exposure dose can limit how small a feature can actually print.
Etch	Removes exposed material using plasma or wet chemistry.	Reactive ion etch to carve a trench or via.	Directional control matters; sidewall damage and roughness become electrical leakage.
Implant / doping	Injects ions to change conductivity or material properties.	Boron for p-type regions, arsenic for n-type regions.	Implant damage must be repaired or activated with a tightly controlled anneal.
Anneal	Heats the wafer to activate dopants and heal damage.	Rapid thermal processing or laser anneal in advanced logic.	Over-anneal widens junctions and can undo the scaling you just paid for.
CMP	Flattens the topography before the next patterning cycle.	CMP after copper fill or STI formation.	Planarity is a prerequisite for later overlay and focus control.
Metrology / inspection	Measures critical dimensions, overlay, thickness, and defects.	Overlay metrology and defect review after EUV patterning.	Process windows are learned by measuring the wafer, not by assuming the recipe worked.
Repeat	Runs the same loop again for the next layer or device region.	A modern chip can require 100 or more layer-printing cycles.	The fab is a closed-loop manufacturing system, not a one-pass assembly line.

Decision guidance: use ALD when conformality and thickness control matter more than throughput; use CVD when a dense, scalable film is needed; use PVD when line-of-sight metal deposition is enough; use etch when you need to transfer the pattern into the underlying material instead of adding another layer.

Lithography

Where the pattern gets defined

Lithography is a projection system. The mask or reticle carries a pattern larger than the chip, optics shrink it onto the wafer, and the same repeat/step cycle is used until the layer is complete.

Technology	What it is	Typical use	Main tradeoff
i-line	365 nm ultraviolet lithography.	Older, simpler, or lower-density layers.	Cheap and mature, but far too coarse for advanced logic layers.
ArF dry DUV	193 nm deep-UV lithography without immersion.	Volume production on less aggressive layers.	Better than i-line, but increasingly limited by resolution and overlay.
ArF immersion DUV	193 nm DUV with water between lens and wafer to improve resolution.	Many high-volume layers on advanced nodes.	Often needs multipatterning; more exposures increase cost and cycle time.
EUV	13.5 nm extreme ultraviolet lithography using mirrors, not lenses.	Critical layers in leading logic and memory nodes.	Vacuum, stochastic resist behavior, masks, and tool cost all raise complexity.
High-NA EUV	0.55 numerical aperture EUV with anamorphic optics.	Next-generation single-exposure scaling for advanced logic and DRAM.	Better resolution, but the tool and process ecosystem are even more expensive and specialized.

Why EUV exists

ASML says EUV makes scaling more affordable and is used for the most intricate layers on a chip. The rest of the stack still uses DUV systems, so advanced fabs run both in parallel.

Example: TSMC’s N2 generation uses EUV on the hardest layers while the rest of the process still depends on mature DUV tools.

Why High-NA matters

High-NA raises numerical aperture from 0.33 to 0.55. ASML shipped the first modules in December 2023 and expects high-volume use in 2025–2026.

Gotcha: High-NA does not replace the entire lithography fleet; it targets the layers where single-exposure patterning is becoming the bottleneck.

Decision guidance: use DUV where throughput and cost dominate, use EUV for the tightest layers where multipatterning becomes too painful, and use High-NA EUV when the next step down in feature size is worth the added tooling and ecosystem cost.

Comparison Tables

Process, packaging, and supply chain roles

Packaging choices

Use this when the board-level story matters more than the transistor pitch.

Package style	Definition	Example use case	When not to use it
Wire bond	Thin wires connect the die pads to the package leads.	Low-cost analog or legacy parts with modest I/O needs.	Avoid when signal density or parasitics are critical; the interconnects are physically long.
Flip-chip	The die is mounted face-down with bumps or pillars.	High-performance CPUs, GPUs, and many mobile SoCs.	Not ideal if package cost and underfill complexity must stay minimal.
Fan-out	Redistributes I/O beyond the die footprint without a traditional substrate.	Thin mobile devices and advanced heterogeneous integration.	Not the first choice when very large compute dies or huge memory stacks need a rigid interposer.
2.5D interposer	Multiple dies sit side-by-side on a silicon or hybrid interposer.	AI accelerators with HBM stacks, such as CoWoS-class packages.	Thermal density and package cost can become the limiting factors before silicon scaling does.
3D stack	Dies are stacked vertically with very short die-to-die interconnects.	Cache-on-logic, memory-on-logic, or tightly coupled chiplets.	Use carefully when heat removal, test access, or yield isolation is more important than bandwidth.

Package decision rule

Use chiplets and 2.5D when a monolithic die is too large for reticle limits, too expensive to yield, or too power-hungry to cool. Use 3D only when latency and bandwidth gains justify thermal and test complexity.

Example: TSMC’s CoWoS integrates logic chiplets and multiple HBM cubes on a silicon interposer for AI and HPC.

OSAT role

Outsourced semiconductor assembly and test companies handle dicing, package assembly, final test, and a growing share of advanced packaging work.

Example: ASE markets advanced heterogeneous integration, chiplet, and silicon photonics packaging.

Supply chain roles

Who does what in the manufacturing ecosystem

Role	Definition	Concrete example	Gotcha
Fabless	Designs chips and outsources wafer fabrication.	An AI chip designer using a foundry PDK and external manufacturing.	The company still owns the design rules, masks, and product architecture even if it owns no fab.
IDM	Designs and manufactures chips in-house.	Intel and Samsung both describe themselves as IDM-style companies.	An IDM can still use foundry or OSAT services; the label is about control, not purity.
Foundry	Manufactures customer designs without selling the finished product under its own name.	TSMC’s pure-play foundry model.	Foundry capacity is only useful if the process design kit and ecosystem are ready for the customer’s design.
OSAT	Assembly and test provider for finished dies and packages.	ASE’s packaging and testing businesses.	Advanced packaging now overlaps with foundry territory, so the boundary is less clean than it used to be.
EDA	Design automation software that turns circuit intent into manufacturable layouts and signoff data.	A 2 nm-class PDK with place-and-route, timing, and DRC flows.	No foundry node is usable without matching design tools and signoff rules.
IP	Reusable functional blocks licensed into a chip design.	Arm CPU cores or physical IP used by fabless customers.	IP support must match the target process node and package strategy, not just the functional spec.
Equipment vendor	Builds the machines that enable deposition, etch, lithography, inspection, and packaging.	ASML, Applied Materials, Lam Research, KLA, ASM.	Tool availability and service capacity can gate output even when the fab shell is finished.
Materials / substrates	Supplies wafers, chemicals, photoresists, gases, and advanced substrates.	300 mm silicon wafer supply plus HBM substrates and interposer materials.	Small chemistry changes can disrupt yield long before they show up in a headline node metric.

Yield and Fab Economics

Why this is so expensive

Yield is the whole game

A wafer only creates value if enough dies pass electrical test at the required speed, power, and reliability. Defect density, die size, overlay error, and process drift all affect the final good-die count.

Example: KLA describes process control as inspection, metrology, and data analysis feeding a repeated correction loop until the wafer reaches a high yield of working die.

300 mm matters because fixed costs dominate

Intel said 300 mm wafers dramatically reduce cost per chip compared with 200 mm. SEMI projected global 300 mm capacity to reach 9.6 million wafers per month in 2026.

Gotcha: bigger wafers do not automatically mean cheaper chips if the yield, utilization, or tool mix is poor.

Economic lever	Definition	Example	Why it matters
Capex	Capital spending on fabs, tools, and infrastructure.	Intel’s Ohio project is >$28 billion; TSMC Arizona’s two fabs were initially about $40 billion.	The first bill is for the building; the real bill is the toolset and the ramp.
Utilization	How fully the installed tools are actually being run.	A fab with excess shell space but underloaded lithography capacity still bottlenecks.	Empty capacity burns depreciation without producing wafers.
Cycle time	How long a wafer spends in the fab before it exits.	EUV can reduce the number of patterning steps versus multipatterned DUV.	Shorter cycle time reduces work-in-process and exposes problems sooner.
Bin spread	Product sorting after test into speed and power grades.	One GPU design may ship in several clock bins once tested and packaged.	A wider spread can help revenue, but it also signals process variation.
Reticle limit	The maximum area that can be printed in one exposure field.	Very large AI dies may move toward chiplets and 2.5D to avoid a monolithic reticle-sized design.	If the die is too big, yield and cost can collapse before performance reaches target.

Decision guidance: use monolithic scaling when the die still fits the reticle and yield curve; use chiplets when the package can recover performance more cheaply than a larger monolithic die. The right answer is almost always a system-level tradeoff, not a transistor-only one.

Current Leading-Edge Landscape

Volatile section

The following items are time-sensitive and should be rechecked before relying on them in a current-state discussion.

Company / platform	Current state as of July 2026	Why it matters	Primary source
TSMC N2 / N2P / A16	N2 entered volume production in 4Q25 with ramp to 100K wafers/month by end 2026; TSMC targets N2P and A16 volume production in H2 2026.	N2 is the first TSMC node with nanosheet transistors, and A16 adds Super Power Rail for denser power delivery.	TSMC N2 page
Intel 18A	Intel says 18A entered production in 2025 and features RibbonFET plus industry-first PowerVia backside power delivery.	18A is Intel Foundry’s leading-edge process and the company’s current showcase for backside power.	Intel 18A page
Samsung SF2	Samsung Foundry says SF2 started mass production in 2025; it extends the MBCFET/GAA line Samsung first put into mass production at 3 nm (SF3E) in June 2022.	Samsung was the first foundry to mass-produce a GAA node, and is positioning SF2 for mobile, HPC, AI, and automotive products.	Samsung logic node page
ASML High-NA EUV	ASML shipped the first High-NA modules in December 2023; Intel began shipping high-volume logic in 2026 using High-NA on select Panther Lake (18A) layers, the first commercial use.	High-NA is the next lithography step for sub-2 nm-class scaling and leading DRAM. Intel's 14A, not 18A, is the first node designed to use it broadly.	ASML EUV systems
TSMC CoWoS	TSMC says CoWoS now serves AI/HPC with large interposers, multiple HBM cubes, and continued roadmap expansion.	Packaging is no longer an afterthought; it is part of the compute product definition.	TSMC CoWoS
Intel EMIB / Foveros	Intel positions EMIB 3.5D and Foveros Direct as a way to combine 2.5D and 3D integration in one package.	That hybrid package approach reduces pressure to fit everything on one die.	Intel packaging page

These facts are the most likely to drift. If you are using this page for current-state planning, re-open the vendor pages first.

Common Mistakes / Anti-Patterns

What trips people up

1. Treating the node number as a literal dimension

The label is a platform generation, not a direct gate-length measurement. Compare the whole process, not the slogan.

2. Assuming EUV replaces DUV

EUV handles the hardest layers, but DUV still prints many layers in every leading fab. The fleets are complementary.

3. Ignoring packaging

Chiplets, interposers, HBM, and thermal constraints can decide the product outcome more than the node label.

4. Thinking more wafers automatically means more chips

Yield, utilization, binning, and packaging capacity determine output, not wafer count alone.

5. Forgetting process control

Inspection and metrology are not support work; they are the feedback loop that keeps the line in spec.

6. Underestimating contamination

At advanced nodes, one particle, mask defect, or residue event can damage multiple layers of output.

7. Overlooking thermal bottlenecks

3D stacking raises bandwidth, but heat removal and test access get harder as stacks get denser.

8. Treating fab economics like ordinary factory economics

Tool mix, lithography availability, and cycle time make semiconductor fabs much more capital-sensitive than most plants.

Primary Sources Used

Official vendor and industry pages